Digital Verification Engineer(J11775)

岗位职责
1. Participate in formulating verification strategies, solutions, and plans at the chip or module level.
2. Use SystemVerilog to build reusable and automated verification platforms for module and subsystem levels.
3. Develop and execute directed or constrained-random tests based on design specifications and architecture documents to achieve comprehensive functional coverage.
4. Define and analyze functional coverage, track code coverage, and ensure verification completeness.
5. Utilize scripting languages such as Python, Perl, or TCL to streamline the verification process and improve regression testing efficiency.
6. Prepare verification plans, verification reports, and technical documentation.

岗位要求
1. Proficient in advanced verification languages, including SystemVerilog and SVA, with hands-on experience in developing verification models using SystemVerilog.
2. Skilled in using simulation and debugging tools such as VCS, Xcelium, and Verdi.
3. In-depth understanding of the digital chip front-end design flow and the overall verification process.
4. Proficient in at least one scripting language (Python/Perl/TCL/Shell) and capable of script development.
5. Proficient in applying the UVM verification methodology; candidates with experience in independently building verification models are preferred.