锦鲤求职岗位描述
Position: Sr. Manager, Physical Design
About Kiwimoore:
Kiwimoore is at the forefront of the semiconductor industry, pushing the boundaries with our innovative Chiplet technology. We are dedicated to advancing computing through a culture of collaboration, innovation, and dynamic teamwork. As part of Kiwimoore, you will join a team committed to redefining the future of semiconductor technology with some of the brightest minds in the industry.
Role Overview:
It is back-end SoC design team covering RTL to GDS methodology, design convergence, and design quality for our projects. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner.
Location: Shanghai
Responsibilities:
In this high impact role on the team, you will be responsible to:
•Own and drive floorplanning and design planning for optimizing large sub-chips and full chip for Area, Power and Performance.
•Experience with Leading Edge SOC Architecture and Landing Zone requirements particularly with high speed fabric and overall protocol and connectivity models.
•Have close collaboration with RTL team to help drive and resolve design issues related to fullchip and block closure.
•Own and drive execution from synthesis to place and route of large sub-chips and/or full chip through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
•Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
•Implement robust clock distribution solutions using appropriate methods that meet design requirements.
•Accurately plan out and clearly communicate block schedules and risks through different project phases.
•Make good independent technical trade-offs between power, area, and timing.
•Provide technical leadership and collaborate across teams to come up with the best solution possible with a One Microsoft mindset.
Qualifications:
Job Requirements
•BS with 12+ years or MS with 9+ years of physical design experience.
Additional Preferred one or more of these Requirements:
•Full Chip/Sub Chip design planning experience using Cadence EDA tools.
•Large SoC design tape-out experience in the latest foundry process nodes.
•Excellent project management skills and ability to juggle multiple projects at once.
•Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
•Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
•Strong understanding of constraints generation, STA, timing optimization, and timing closure.
•In-depth understanding of design tradeoffs for power, performance, and area.
•Solid hands on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs.
•Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, Innovus etc.
•Experience and knowledge of formal equivalency checks, LP, UPF, reliability, SI, and noise.
•Strong problem-solving and data analysis skills
•Strong automation skills using scripting languages such as Perl, TCL, Python.
What Kiwimoore Offers:
1.A competitive salary and comprehensive benefits package.
2.Career growth opportunities in an innovative and dynamic field.
3.A creative, inclusive, and collaborative work environment.
4.The opportunity to be part of a pioneering team revolutionizing technology.
How to Apply:
If you are a dynamic professional looking to impact the tech world , apply now! Submit your application through our careers page, including a resume and a cover letter explaining why you are the perfect fit for the Sr. Manager, Physical Design at Kiwimoore.
Kiwimoore is an equal opportunity employer. We value diversity and are committed to creating an inclusive environment for all employees. All employment is decided based on qualifications, merit, and business need.