岗位描述
Job Responsibilities:
• The candidate will be responsible for leading and driving large designblocks from early design stage to tape out.
• Work responsibilities include synthesizing extremely high speed designs, following through with Place and Route and analyzing design results, and making changes to the RTL code as needed.
• Should be able to read RTL and understand the micro architecture of the blocks if needed perform RTL modifications
• Should be able to partition, floorplan, do LEC at the SoC level designs
Job Requirements:
• BS with 3+ years or MS with 1+ years of physical design experience.
Additional Preferred one or more of these Requirements:
• VLSI/IC design experience in a professional environment
• Knowledge of Logic Design and Synthesis
• Key electrical analysis like IR drop/EM and timing analysis concepts
• Auto P&R background and skills
• Experience with Timing Closure, Circuit Design, Electrical Closure, and Memory Compiler Work
• Proven understanding of RTL, microarchitecture, Physical DesignCAD tools and scripting languages (Perl or Python)